EDN

Chip-scale packaging comes of age for power devices

The benefits of chip-scale packages are fairly obvious. In space-constrained, very dense designs, every bit of board space is precious. Chip-scale packaging, which eliminates the extra space along the ...
EDN

Chip-scale powers MOSFET packages

The best-performing and most cost-effective power MOSFETs might well turn out to be those having no package at all. With power-MOSFET silicon now largely optimized, manufacturers are quickly ...
Semiconductor Engineering

High Performance, Multi-Chip Leadframe Package With Internal Connections

For high performance applications, demand for highly integrated packages has increased. This is due to the highly integrated package’s electrical performance advantages of reduction of interchip ...
Nasdaq

Akoustis Locks Process Flow for First Wafer-Level-Chip-Scale Package (WLCSP) for XBAW Filters

Charlotte, N.C., Feb. 01, 2021 (GLOBE NEWSWIRE) -- Akoustis Technologies, Inc. (NASDAQ: AKTS) (“Akoustis” or the “Company”), an integrated device manufacturer (IDM) of patented bulk acoustic wave (BAW ...
CNET

Can Tessera pack an IPO punch?

As cell phones and other devices get smaller but more powerful, chip packaging is taking on increased importance. And Tessera Technologies holds some important patents. Michael Kanellos is editor at ...
Semiconductor Engineering

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology

How a real chip-last process flow with a chip-to-wafer (C2W) bonding technology can address the RDL-base Interposer PoP challenge. Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has ...