Semiconductor Engineering

Design Flow Challenged By 3D-IC Process, Thermal Variation

3D-ICs are proving a challenge even for designers accustomed to dealing with power and performance tradeoffs, but they are considered an inevitable migration path for leading-edge designs due to the ...
EDN

TSMC Unveils IC Design Flow For 0.25-, 0.18-Micron Processes

Taiwan Semiconductor Manufacturing Co. (TSMC) today released what it believes is the first manufacturability-focused IC design flow that is silicon-proven in its 0.25-micron and 0.18-micron ...
Business Wire

Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a node-to-node design migration flow based on the Cadence ® Virtuoso ® Design ...
Business Wire

Cadence Full-Flow Digital and Signoff Tools Certified on Samsung Foundry’s 7LPP Process Technology

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s ...
Design-Reuse

Synopsys IC Compiler Enables Fully Automated 65-Nanometer Implementation Flow For ARM Cortex-A8 Processor

Flow delivers a 5-10X boost in productivity for mobile and consumer applications MOUNTAIN VIEW, CA AND CAMBRIDGE, UK—Mar. 28, 2007—Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor ...
Business Insider

New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board

Solution integrates the Virtuoso platform with Allegro and Sigrity technologies to streamline overall design process and significantly improve productivity and cycle time SAN JOSE, Calif., May 30, ...
Design-Reuse

Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology

SAN JOSE, Calif., 17 Oct 2019-- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the complete, integrated Cadence ® 3D-IC advanced packaging integration flow has achieved certification ...
EDN

UMC certifies Cadence 3D-IC reference flow

Speeding time to market, the Cadence 3D-IC reference flow, featuring the Integrity 3D-IC platform, has been certified for UMC’s chip stacking technologies. UMC’s hybrid bonding solutions support the ...
New Electronics

Tower and Cadence unveil 5G and automotive IC reference flow

Cadence Design Systems and Tower Semiconductor have jointly released a silicon-validated SP4T RF SOI switch reference design flow that uses Cadence's Virtuoso Design Platform and RF Solution. The ...
Water Technology

A new era of semiconductor water management: Challenges, constraints and cutting-edge solutions

As chip manufacturing scales up, water supply and wastewater treatment systems are under immense pressure. Cutting-edge ...
Semiconductor Engineering

3D-IC Standardization Progress Continues

Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and ...