Semiconductor Engineering

System-Level, Post-Layout Electrical Analysis For High-Density Advanced Packaging

As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides ...
EDN

Silicon Frontline Technology’s first tools verify IC post layout

Startup Silicon Frontline Technology, Inc. has anounced its first products for post-layout verification: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of ...
EDN

Springsoft integrates Edxact’s post-layout analysis tool

PARIS — On the eve of the Design Automation & Test in Europe Conference, from March 8 to 12, 2010, in Dresden, Germany, edXact SA (Grenoble, France) said it has integrated its Comanche post-layout ...
Business Wire

EDXACT's JIVARO Tools Qualified by ST for Post Layout Simulation Flow

GRENOBLE, France--(BUSINESS WIRE)--July 24, 2006--EDXACT today announced that STMicroelectronics has added EDXACT's JIVARO parasitic reduction tools to its Post Layout Simulation flow (PLS), in order ...
Semiconductor Engineering

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers ...
Design-Reuse

A point of view on ''Analog Design and Layout Migration automation in the AI era''

The design teams typically invest years and numerous iterations to validate IP and produce a functioning chip. Once this validation is complete, they create derivatives of the silicon-proven IP, often ...